Integrated circuit (“IC”) designers desire to increase the level of integration, or density, of features within an IC by reducing the size of individual features and by reducing the separation distance between adjacent features on a semiconductor substrate. The continual reduction in feature size places ever-greater demands on techniques used to form the features, such as photolithography. This trend in increasing integration is also accompanied by a corresponding decrease in feature dimensions, which makes electrical isolation of the features an important aspect in fabricating semiconductor structures or semiconductor devices.
The trend is of particular relevance in the manufacture of memory devices, such as dynamic random access memory (“DRAM”) memory devices. A typical memory cell, such as a DRAM cell, includes a transistor and a memory storage structure, such as a capacitor. Semiconductor devices typically include large numbers of DRAM cells. As the dimensions of individual memory cells in a DRAM array shrink, adjacent or neighboring gates become closer together and the need for efficient and reliable isolation processes to separate active regions, such as the transistors, of the DRAM cell dramatically increases. Known fabrication processes for producing memory cells and other devices having sub-micron dimensions have become increasingly inefficient. One method of isolating the transistors of the DRAM cell is to form a trenched isolation region between adjacent active regions of the DRAM cell. The trenched isolation region typically includes a trench or cavity formed within the substrate and filled with an insulative material, such as silicon dioxide (“SiO2”). The trenched isolation region is typically formed between neighboring transistors. However, as feature sizes continue to decrease, electrical operation of the transistors becomes more difficult. One contributing factor to this difficulty is known as the so-called “short channel effect” in which the width of the transistor channel becomes excessively small due to miniaturization, which results in the transistor activating even if a threshold voltage (“Vt”) has not been applied to the gate. Another method of providing isolation is to appropriately dope the memory device. However, depending on the structure of the memory device, effective doping may be costly or may not be possible.
One example of a transistor that has been developed to overcome the short channel effect of a conventional transistor by forming a wider channel in the same horizontal space is a recessed access device (“RAD”) transistor. One example of a RAD transistor includes a transistor gate (wordline) which is partially formed within a trench in a semiconductor substrate. The channel region is formed along the entire surface of the trench which, in effect, provides a wider channel without increasing the lateral space required by the transistor.
Memory device structures and methods of forming memory device structures are also described in U.S. Pat. No. 7,098,105 to Juengling and United States Patent Application Publication No. 2006/0046407 to Juengling, each of which is assigned to the assignee hereof and the disclosure of each of which is incorporated by reference herein in its entirety. The memory device structure includes a gateline lattice surrounding a plurality of source/drain regions. A gateline material forms the gateline lattice and the source/drain regions form an array with repeating regions spaced from one another by segments of the gateline lattice. The memory device structure is incorporated into a DRAM array by forming digit lines over and in electrical connection with some of the source/drain regions and by forming a plurality of capacitors in electrical connection with some of the source/drain regions. The memory device structure includes a substrate, a pair of so-called “pedestals,” “pillars,” or “fins” of semiconductor material, the gateline material located between the pedestals, and a gate dielectric material. One of the pedestals corresponds to the source/drain region utilized to electrically connect to the digit line, and the other pedestal corresponds to the source/drain region utilized to electrically connect to the capacitor. The gateline material between the pedestals functions as a transistor gate of a transistor device, which gatedly connects the source/drain region associated with one of the pedestals with the source/drain region associated with the other pedestal.
During fabrication of the memory device structures described in U.S. Pat. No. 7,098,105 and United States Patent Application Publication No. 2006/0046407, etch processes are used to form openings in the substrate. The gateline material is subsequently deposited in the openings. At larger feature dimensions, the etch process is capable of forming openings having substantially vertical sidewalls. However, as the feature dimensions decrease, the etch process is not capable of forming openings having substantially vertical sidewalls. Rather, as the feature dimensions continue to decrease, the fabrication processes described in U.S. Pat. No. 7,098,105 and United States Patent Application Publication No. 2006/0046407 may form pedestals or fins 2 in the substrate 6 having sloped sidewalls 4, as shown in FIG. 1. Since a substantially vertical etch of the substrate 6 is no longer possible when forming features having smaller dimensions, the sloped sidewalls 4 of the fins 2 are caused by forming the openings having sloped sidewalls. When the gateline material 8 is conformally deposited in these openings to form the gates, the deposited gateline material 8 also has sloped sidewalls, which reduces isolation and causes shorting between the gates. Fins 2 having sloped sidewalls of as little as 5°-6° may cause isolation and shorting problems.
Thus, there is a need in the art for developing fabrication processes to produce semiconductor structures similar to those described in U.S. Pat. No. 7,098,105 and United States Patent Application Publication No. 2006/0046407, but exhibiting improved isolation and reduced or eliminated shorting problems, for utilization in memory device structures.